1. The Field of the Invention
The present invention relates to a local interconnect in an integrated circuit, and particularly to a method of making a local interconnect structure situated on an active area within a semiconductor substrate, where the lo,al interconnect has tungsten silicide and titanium nitride layers, or has a tungsten layer covered on opposite sides thereof with titanium nitride.
2. The Relevant Technology
Local interconnects are normally used when a metalization is not being used to electrically connect semiconductor devices. A lo, al interconnect is used, for example, to put a conductive material in electrical contact with an active area in a semiconductor substrate. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above.
Typical local interconnects comprise materials such as titanium nitride, titanium silicide and other kinds of low resistance materials such as refractory metal suicides. Typically, after the gates and transistors and other topographical structures are defined, a refractory metal film is formed thereover either by sputtering, also known as physical vapor deposition process, or by chemical vapor deposition (CVD). Sputtering titanium nitride film is characterized by low resistivity with poor step coverage. As a result, sputtered titanium nitride film is difficult to use in circuits and devices with vertically oriented topographies. Sputtering produces a titanium nitride film with a lower resistivity than CVD titanium nitride, but has a poorer step coverage over vertically oriented topographies.
In situations where a hard mask is needed in the formation of an interconnect structure, hard masks have typically been comprised of polysilicon or silica. In a contact etch, the hard mask need not be removed if the contact etch can etch through the hard mask and stop etching on an underlying local interconnect without compromising active areas. If the contact etch can not etch through the hard mask without deleterious effect, then the hard mask should be removed during fabrication of the interconnect structure, and such removal can be difficult to properly achieve.
Another problem with a polysilicon or oxide hard mask is that typical etches are not selective to these types of hard masks, and where the hard mask is not a conductive material, it tends to oxidize. If the etch etches through the hard mask and underlying layer(s) of a local interconnect, the etch can potentially damage the active area. If so, removal of the hard mask is desirable. One removal method for polysilicon or silica hard mask is a wet etching process. The etching process, however, is not desirably selective to polysilicon or to silica. This results in difficulty in controlling the etch, which difficulty can result in a low yield rate due to an over etching into an underlying active area in the semiconductor substrate.
Typically, refractory material nitrides are used as a barrier layer. For example, the nitrides include titanium nitride and tungsten nitride. It is difficult to stop an etch on a nitride. If the etch is too deep and goes through beyond the nitride, the active area can be compromised. Titanium nitride, as such, is not a preferred material for a dry etching process for a selective etch. To compensate, a type of material is put down that can be patterned, such as a photoresist layer through which the titanium nitride can be selectively removed without a hard mask. It is difficult, however, to control the etch of the titanium nitride without any kind of hard mask, and such difficulty of control may result in an etch through the titanium nitride layer and into the underlying active area.
It may be desirable to use two etchants, such as one to etch a first interconnect material and another to etch the titanium nitride in contact therewith. For example, it titanium nitride and titanium silicide are the layers; of the interconnect structure, the titanium silicide can be etched with an hydrofluoric chemistry etch, but the etch will not substantially etch the titanium nitride. Consequently, a second etch is needed that will etch the titanium nitride, where the second etch is selective to titanium silicide.
It would be advantageous to overcome the problems of poor step coverage and uncontrolled etching, and to be able to use one etchant to remove both the interconnect material and an associated barrier layer. In addition, it would be advantageous to utilize a material which also provides an improved step coverage in the fabrication of the interconnect structure.
Additional advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.
In accordance with the invention as embodied and broadly described herein, a method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. The semiconductor substrate comprises a silicon base layer that includes active areas therein and has gate stacks thereon.
A hard mask layer is then formed over the first barrier layer and multilayer structures using chemical vapor deposition. The hard mask layer comprises CVD tungsten silicide and provides good step coverage. The first barrier layer also provides adhesion of tungsten silicide to the semiconductor substrate and to the field oxide region. A photoresist layer is then formed over the hard mask layer. The hard mask is selectively removed from above an adjacent multilayer structure using a chemical etch that is selective to the first barrier layer so as to expose the first barrier layer. The first barrier layer is then selectively removed from a surface of the adjacent multilayer structure using) a chemical etch that is selective to the tungsten silicide of the hard mask layer. A passivation layer, composed of silica for example, is formed over the hard mask layer. A recess is formed in the passivation layer that is generally aligned with an active area in the semiconductor substrate adjacent to the adjacent multilayer structure. The recess is substantially filled with an electrically conductive material. A planarizing operation is conducted to isolate other electrically conductive material within other recesses one from another.
A second method of forming a local interconnect structure is also provided. The second method comprises forming a first barrier layer comprising sputtered titanium nitride over a semiconductor substrate having topographical structure. The semiconductor substrate comprises a silicon base layer that includes active areas therein and has gate stack thereon. A first electrically conductive layer that comprises CVD tungsten is then formed over the first barrier layer. The first electrically conductive layer provides good step coverage. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer.
A hard mask layer is then formed over the second barrier layer. The hard mask is composed of a material such as polysilicon, silicon dioxide, or tungsten silicide. The hard mask is selectively removed above an adjacent multilayer structure using a chemical etch selective to the second titanium nitride barrier layer. The second barrier layer, the first conductive layer, and said first barrier layer are ,electively removed using a chemical etch comprising an ammonium peroxide mixture selective to the hard mask layer. The ammonium peroxide mixture comprises ammonia, peroxide and water in a ratio of 1:1:5 by volume and is used at a temperature of about 65xc2x0 C. A silica layer substantially is then formed over the semiconductor substrate. A recess is formed in the silica layer that is generally aligned with an active area within the semiconductor substrate. The recess is substantially filled with a second electrically conductive layer thereby forming a contact through at least the second barrier layer, the first conductive layer, and the first barrier layer to the active area in the semiconductor substrate. A planarizing operation is conducted to isolate other second electrically conductive layers within other recesses one from another.